Media Alert: Atomera to Highlight Advances in 4F² DRAM Transistors and GaN Devices at SISPAD 2026

Albert Lu, Staff Engineer, Atomera

In-person paper presentation entitled “Enabling 4F² DRAM Junctionless Vertical Channel Transistors with Novel Oxygen Inserted Si Substrates” (Room A1, 3rd Floor)

The presentation details a TCAD simulation study examining a fundamental architecture shift in DRAM scaling: the transition from the conventional 6F² cell to the 4F² cell built around a Vertical Channel Transistor (VCT). This transition demands sufficient on-state drive current for read/write operation, elimination of the Floating Body Effect (FBE), and off-state leakage low enough to meet retention-time targets. The study shows that MST’s predefined doping layers in the silicon substrate enable a junctionless VCT architecture for 4F² DRAM cells. By precisely controlling the doping profile and dopant out-diffusion, MST satisfies these read/write current and data retention requirements while simplifying the process flow and reducing selective epitaxial steps, offering a simpler, more scalable, lower-cost path to multiple 4F² DRAM nodes.

Sunday, September 27, 2026 at 10:30 p.m. to 10:50 p.m. PDT (Monday, September 28, 2026 at 2:30 p.m. to 2:50 p.m. JST)

Dr. Ilya Rumyantsev, Principal Engineer, TCAD Modeling, Atomera

In-person poster entitled “Physics-Informed Compact Modeling of Off-State Leakage and Breakdown in GaN-on-Si Devices” (Room A3-A4)

The poster introduces a compact model of off-state leakage and breakdown in GaN-on-Si high-electron-mobility transistors (HEMTs). It compares devices built on conventional silicon, high-resistivity silicon, and Atomera’s MST-modified silicon. The data show that the MST devices have lower low-voltage leakage and a delayed high-field current rise compared to the conventional control. High-resistivity silicon behaves differently, while interface measurements indicate that MST modifies the buried AlN/Si interface. The model reproduces these behaviors, providing a practical framework for comparing process splits, localizing where leakage changes, and guiding further MST and GaN-on-Si development.

Tuesday, September 29, 2026 at 12:00 a.m. to 2:00 a.m. PDT (Tuesday, September 29, 2026 at 4:00 p.m. to 6:00 p.m. JST)

3-40, Sakuramachi, Chuo-ku, Kumamoto-city,

Kumamoto, 860-0805, Japan